This application note discusses the design techniques and performance of the Hewlett-Packard AT-3 series of silicon bipolar transistors as used in typical low noise amplifiers for use in the various commercial markets. Although specific designs are presented for 900 and 2400 MHz, the techniques are applicable to other applications in the VHF through S Band frequency range. 900 and 2400 MHz Amplifiers Using the AT-3 Series Low Noise Silicon Bipolar Transistors This would include the 450 MHz (Mobile Radio), 900 MHz (Cellular and Pager), 1.2 and 1.5 GHz (GPS), 1.9ÊGHz (PCN), 2.1 to 2.7 GHz (MMDS and ITFS) and the 2.4 GHz (ISM) markets. Generally, silicon bipolar devices are easier to work with at the lower frequencies because of their inherently lower impedances. However, today’s state-of-the-art low current bipolar transistors have considerably higher impedances making them comparable to GaAs FETs at these frequencies. Similar design techniques must be used with these devices to assure good performance. Appropriate design techniques will be presented. This application note will begin with an overview of noise parameters and definitions and then lead into general design considerations for building low noise amplifiers. Two amplifier designs will be presented along with measured results. The application note will finish with a discussion of matching network losses and their effect on amplifier noise figure. TouchstoneTM circuit files and simulated results for both amplifiers are included in the Appendix. 2. Noise Parameter Measurements A typical test set-up for measuring noise parameters is shown in Figure Ê1. The device under test (DUT) is normally inserted into a test fixture that includes 50 ohm input and output transmission lines whose effect can be calibrated out for the particular frequency. As a minimum, a double stub tuner or Figure 1. Typical Noise Parameter Measuring Test Set-up. NOISE SOURCE BIAS TEE BIAS TUNER TUNER TEE NOISE FIGURE METER ISOLATOR DEVICE UNDER TEST FMIN.Ga RN ADJUST FOR MINIMUM NF ADJUST FOR MAXIMUM GAIN SUPPLES GATE VOLTAGE OR BASE CURRENT SUPPLIES DRAIN VOLTAGE OR COLLECTOR VOLTAGE O 5964-3854E 4-5 equivalent must be used at the input to the DUT to present the required Gamma Opt., O, to the device for it to achieve its minimum noise figure. Although not always required, a tuner can be inserted at the output of the DUT. Providing a conjugate match at the output of the DUT while the input is presented with O provides a means of measuring associated gain at minimum noise figure. One particular manufacturer of automatic noise measuring equipment uses a tuner on the input and terminates the output in 50 and then measures the resultant S22. A calculation then provides the associated DUT gain. Bias Tees are used at the input and output of the DUT to bias the device. A noise source with a low Excess Noise Ratio, ENR, such as the Hewlett- Packard HP346A, is desired as it minimizes test error by minimizing the range over which the noise figure meter must remain linear. The HP346A noise source also has minimal change in reflection coefficient between the “on” and “off” states. This minimizes the ability of the DUT to change its gain with varying input termination. Any change in DUT gain will increase the measurement error. An isolator placed at the input of the noise figure meter is always desirable but may not be possible at the lower frequencies where size becomes more of an issue. The noise figure of a linear two port is given by equation (1) shown in the table below. In equation (1), NFmin is the device minimum noise figure when terminated in Yon, Yon is the generator admittance at which minimum noise figure occurs, Yg is the generator admittance presented to the input of the device, Rn is the noise resistance which gives an indication of the sensitivity of noise figure to termination, and Gg is the real part of the generator impedance. The equation can be transformed into an equivalent equation involving the source reflection coefficient, S, and the reflection coefficient required for minimum noise figure, O. See equation (2) below. Once O has been determined and NFmin determined, the Rn can be determined by making a 50 noise figure measurement and calculating Rn. This procedure only works well if O can be determined by a single measurement. A more accurate method would be to pick 4 reflection coefficients (4 terminating impedances) in the vicinity of where one believes O to be and then solve 4 equations and 4 unknowns. This method has become a more accurate industry standard. The input tuner must be capable of transforming the customary 50Êohm source impedance to that required for the device to achieve its rated noise figure. As an example, for the Hewlett-Packard AT-30511 operated at a VCE of 1 volt and IC of 1 mA, O has a magnitude of 0.76 increasing to 0.96 at 500 MHz. These numbers represent impedances that can be increasingly difficult to match with low loss. Losses of the tuner become more questionable as the O increases, plus the ability to design and build a low loss matching network becomes more of a challenge. An early paper by Strid[1] discusses tuner losses as well as losses in matching networks. The problem with tuner losses is that the tuner has a different loss for every tuner setting and this effect is more pronounced at higher reflection coefficients. The user must rely on calibration data supplied by the manufacturer and this data may not be guaranteed much above a reflection coefficient of 0.6 to 0.7. If the tuner’s calibration were accurately known and relatively constant with tuner setting then it would be a simple matter to adjust the tuner and DUT for lowest noise figure and then subtract out the tuner loss to obtain the DUT minimum noise figure, NFmin. With varying loss in the tuner, it is difficult to determine if adjusting the tuner and DUT for minimum noise figure minimizes the DUT noise figure or the tuner loss. The alternative of presenting 4 known impedances to the device and solving 4 equations and 4 unknowns is preferred. NF = NF + NF = NF + R G Y – Y 2 (1) 4 R Z - 2 ( 1 + 2 2 ) (1 – ) min (2) min n n o s s o o g g on Equations 4-6 3. General Design Considerations Implementing the input match can take on any of a variety of circuit topologies depending on the frequency and the space allowed for implementing the network. Alternatives may include: • Lumped element network, • Microstripline network, or • Cavity filter match A lumped element network can be either high pass, low pass, or bandpass and generally 2 or 3 elements. Below 2 GHz these networks will generally be lower loss than a microstripline circuit because of substrate losses. Above 2 GHz, the lumped element topology will be very difficult to synthesize with realizable components. The cavity filter approach is probably the lowest loss matching network but cost and size generally make it prohibitive for most commercial applications. Losses of actual input matching circuits have been measured at nearly 0.5 dB at VHF frequencies when attempting to match the high impedances of MESFETs. Similar impedances can be encountered when using low current silicon bipolar transistors. Matching a device for lowest noise performance does not necessarily guarantee the best input VSWR and performance tradeoffs need to be made. A solution is the use of inductance in the emitter leads to create negative feedback which can bring O and S11* closer in value[2,3,4]. The amount of inductance must be carefully weighed against its effect on other circuit parameters such as gain and stability. An improperly chosen amount of inductance can cause out-ofband oscillations that can prohibit an amplifier from delivering its rated performance. Other techniques such as resistive feedback and resistive loading can improve stability but can limit power output capability. An often overlooked part of an amplifier is the bias decoupling network that must be invisible to the RF matching networks. Generally they provide a low loss method of biasing the devices but in some situations can actually be used to provide some resistive loading for stability both in-band and out-of-band. Properly designed bias decoupling networks can also be used to provide some form of band pass or high pass filtering that could help reduce low frequency out-of-band gain. A poorly designed amplifier with very high low-frequency gain that may be unconditionally stable according to the computer simulation may actually oscillate if the output can radiate back to the input. The enclosure that houses the amplifier must be designed to offer enough isolation around the circuit such that it does not make the amplifier circuit unstable at any frequency. The manner in which circuit elements are implemented will affect the overall amplifier performance. The use of etched circuit elements as opposed to surface mount discrete elements offers a cost benefit but may affect losses. Surface mount components offer small size but parasitics and device Q must be understood if their effect on circuit performance is to be properly analyzed. 4. 900 MHz Silicon Bipolar Amplifier The 900 MHz amplifier uses an AT-32033 which is in the industry standard SOT-23 package. The AT-32033 is one of a series of silicon bipolar transistors that are fabricated using an optimized version of Hewlett-Packard’s 10 GHz ft Self-Aligned-Transistor (SAT) process. The die are nitride passivated for surface protection. Excellent device-to-device uniformity is guaranteed in fabrication by the use of ion-implantation, self aligned techniques, and gold metalization. The AT-3 series of devices has a 3.2Êmicron emitter-to-emitter pitch and has been fabricated in a variety of geometries for various applications. The 20 emitter finger interdigitated geometry yields an easy to match device capable of moderate power at low to moderate current. The 10 emitter finger geometry offers higher gain at low current while the 5 emitter finger geometry offers the highest gain at lowest current consumption. The smaller devices at very low current present very high impedances that can make them more of a challenge to design with. The impedances associated with very low current transistors at 900 MHz are very similar to those presented by 500Êmicron MESFETs at 900 MHz. The 900 MHz AT-32033 amplifier is designed for a nominal 1 dB noise figure and 10 dB associated gain at 2 mA collector current. Although the device is capable of sub 1 dB noise figures, most applications do not require much below 1.5 dB. Starting out with a device that has such a low NFmin allows the designer to make tradeoffs between noise figure, gain, stability, etc. The schematic diagram of the 900ÊMHz amplifier is shown in Figure 2. The input noise match consisting of a low pass network in the form of C2 and Z1 provides a low Q broad band match. A small wound inductor could replace 4-7 transmission line Z1. A value in the range of 15 to 20 nH would be a good substitute. In the actual circuit it was found that the input shunt capacitor was not required. Adding a shunt capacitor at this point will allow the designer to make tradeoffs between noise figure and input VSWR. The output match consists of a 3Êelement low pass network. The 3Êelement network allowed a shorter length of series transmission line to be used as compared to a 2 element match. The series inductive element can be etched onto the printed circuit board or a low cost wound inductor can be used if board space is limited. A suggested value would be in the range of 20 to 25 nH. The artwork and component placement guide are shown in Figures 3 and 4. A small amount of emitter inductance is used to improve in-band stability. This value must be carefully chosen such that an excessive amount is not used, otherwise high frequency oscillations could be produced. Out-of-band oscillations will severely limit the ability of the device to produce its rated performance. Resistor R1 provides very low frequency stability while resistor R5 enhances overall stability, including in-band performance. A current source consisting of resistor R2 connected to the resistive divider consisting of resistors R3 and R4 provide the necessary base current to produce the desired 2ÊmA collector current. Actual measured noise figure of the amplifier with a micro-stripline input is shown in Figure 5. The amplifier provides a nominal 1.25 dB noise figure from 800 to 1000 MHz. The noise figure will improve slightly with the use of a wound inductor in place of the microstripline. Pay careful atten- Figure 2. Schematic Diagram of AT-30233 900 MHz Amplifier. The etched microstriplines can be replaced by a pair of lumped inductors as shown in Figure 7 with a 0.1ÊdB improvement in noise figure. Once the circuit has been optimized for best noise figure, gain and input/ output VSWR, it is then necessary to take a look at output power. The 900ÊMHz amplifier was first tested for P1dB and then for IP3. Initial results for P1dB were less than those as specified on the data sheet. The major difference is that the amplifier being evaluated was conjugately matched at the output. Most device manufacturers specify P1dB at a “power match” and not a “conjugate match”. This implies that tuners are used at the input and output of the device to maximize tion to the parasitic capacitance of the wound inductor as it could limit amplifier noise figure and affect out-of-band stability. Actual measurements of the microstripline input match circuit indicates a 0.26 dB loss. Subtracting this loss from the measured amplifier noise figure suggests a 1ÊdB device noise figure which is as predicted by the computer simulation. One of the advantages of using a device with a 0.78 dB NFmin is that compromises can be made between noise figure, gain, and input match. Actual measured amplifier gain is shown in Figure 6. The amplifier has a nominal 11 dB gain from 750 to 900ÊMHz. INPUT Zo C1 Vcc C2 Z1 R1 Z3 C3 R2 R3 R4 C7 Q1 C5 Z2 C4 OUTPUT R5 Z4 C1–10 pF CHIP CAPACITOR C2 – 1 pF CHIP CAPACITOR (ADJ FOR NF/VSWR) C3, C7–1,000 pF CHIP CAPACITOR C4–100 pF CHIP CAPACITOR C5–1 pF CHIP CAPACITOR C6–2.7 pF CHIP CAPACITOR Q1 – HEWLETT-PACKARD AT-32033 SILICON BIPOLAR TRANSISTOR R1 – 50 OHM CHIP RESISTOR R2 – 47 K OHM CHIP RESISTOR (ADJ FOR RATED Ic) R3, R4 – 15 K OHM CHIP RESISTOR R5, – 150 – 180 OHM CHIP RESISTOR (ADJ FOR STABILITY/POUT) Zo – 50 OHM MICROSTRIPLINE Z1–Z2 – ETCHED MICROSTRIPLINE CIRCIITRY (MAY SUBSTITUTE INDUCTOR) Z3–Z4 – MICROSTRIP BIAS DECOUPLING LINES C6 Zo 4-8 Figure 3. 2X artwork for 900 MHz Amplifier using 0.062 inch thick FR-4. Figure 4. Component Placement for 900 MHz Amplifier using 0.062 inch thick FR-4. 12 8 10 6 2 4 0 GAIN, dB 750 800 850 900 950 1000 FREQUENCY, MHz Figure 6. AT-32033 Amplifier Gain. Figure 5. AT-32033 Amplifier Noise Figure. 2.0 1.5 1.0 0.5 0 NOISE FIGURE, dB 700 750 800 850 900 950 1000 FREQUENCY, MHz WARNING: DO NOT USE PHOTOCOPIES OR FAX COPIES OF THIS ARTWORK TO FABRICATE PRINTED CIRCUITS. gain and power output. Maximum power output rarely occurs when any device’s output port is conjugately matched. How much improvement can be achieved by power matching? Initially, the 900 MHz amplifier was tuned for best output VSWR at 850ÊMHz. Greater than 20 dB return loss was obtained. The measured 1ÊdB compression point referenced to the output was -5.5 dBm with the device biased at a VCE of 2.7 volts and 2 mA IC. Close examination of the output matching network suggested that possibly the 180 resistor used in the output bias decoupling line might be 4-9 absorbing some of the power. This resistor was placed in the circuit to raise in-band stability. Placing a short across this resistor and remeasuring the 1 dB compression point showed an improvement of 3.5 dB! Also observed was an increase in collector current when the device is driven toward compression. An increase in current causes an increase in the voltage drop across the 180 resistor causing the collector voltage to sag. Minimizing the value of this resistor will tend to keep VCE high when the device is driven hard and will also minimize power absorption in the circuit. The drawback could be decreased stability. Some compromise with respect to output loads may have to be instituted if additional power output is desired. A P1dB of -2 dBm is still slightly lower than the data sheet specification. However, the output is still conjugately matched and not power matched. In order to provide a power match, one must provide an alternative output match. In order to prove that a power match will provide greater power output, a lab exercise can be setup. A double stub tuner is connected in series with the existing conjugately matched amplifier output circuitry and the power meter. The tuner is then adjusted for greatest power output while driving the input circuit higher. A spectrum analyzer can be useful here to determine that harmonics are not high enough in level to distort the power meter measurement. In small steps increase the input power and then retune the output tuner for maximum fundamental power. After retuning the output for a power match, it was found that the P1dB increased to nearly 2ÊdBm with a reduction in gain of 1ÊdB over the small signal conjugate match. In order to revise the output match to provide a power match would require breaking the circuit at the collector port of the device and measuring the new Gamma Load (L) presented by the existing circuit plus the external tuner. It is interesting to note that the output return loss which was greater than 20 dB at 850 MHz is now only 8.5 dB at the power match condition. In addition to measuring P1dB at all output matches, the two tone third order intercept point (IP3) was also measured. For each test, two tones were introduced at the input to the amplifier which are separated by 10ÊMHz. The resultant third order products were then measured and averaged and IP3 was calculated. The results are shown in Table 1. The results show a consistent 20 to 21 dB of difference between P1dB and IP3. This is somewhat greater than has been measured on other larger geometry small signal devices but it does appear to be repeatable. 5. 2400 MHz Silicon Bipolar Amplifier The 2400 MHz amplifier is designed around the Hewlett-Packard AT-31011. The 10 emitter finger geometry plus the SOT-143 package with the two emitter leads offers improved performance at frequencies above 2 GHz. At a rated current of 1ÊmA, the AT-31011 provides a device noise figure of 1.7 dB at 2400 MHz with an associated gain of 10 dB. The schematic diagram of the 2400ÊMHz amplifier is shown in Figure 8. The input noise match consisting of a low pass network in the form of C2 and Z1 provides a low Q broad band match. The capacitor at C2 can be optimized for either a noise or conjugate match. The output match consists of a 2 element low pass network while the interstage network consists of two short transmission lines and a series capacitor. The artwork and component placement guide are shown in Figures 9 and 10. Minimal emitter inductance is used to preserve in-band gain without sacrificing stability. Resistor R1 provides low frequency stability while resistors R5 and R10 enhance overall stability, including in-band performance. Two current sources (resistor R2 connected to the resistive divider consisting of resistors R3 and R4 and R7 connected to the resistive divider consisting of R8 and R9) provide the necessary base current to produce the desired 1 mA collector current in each device. Condition P1dB IP3 Conjugate Match -5.5 dBm +16 dBm Conjugate Match w/o resistor – 2.0 dBm +18 dBm Power Match +2 dBm +23 dBm Table 1. 900 MHz Amplifier Power Output Summary. Figure 7. 900 MHz Amplifier showing the Placement of Wound Inductors in place of Microstripline Networks. 4-10 Figure 8. Schematic Diagram of AT-31011 2400 MHz Amplifier. Figure 9. 2X artwork for 2400 MHz Amplifier using 0.062 inch thick FR-4. Figure 10. Component placement for 2400 MHz Amplifier (Drawing not to scale). INPUT Zo C1 Zo Vcc Vcc C2 Z1 Z5 C5 C6 C7 Q1 Z2 C3 Z3 R5 Z6 R6 Z7 C8 Q2 Z4 C4 OUTPUT C1, C4, C5, C9 –10 pF CHIP CAPACITOR C2 – 1.3 pF CHIP CAPACITOR C3–1.5 pF CHIP CAPACITOR C6, C7, C8, C10,–1,000 pF CHIP CAPACITOR C11– 2 pF CHIP CAPACITOR (ADJUST FOR MIN OUTPUT VSWR) Q1, Q2 – HEWLETT-PACKARD AT-31011 SILICON BIPOLAR TRANSISTOR R1, R10 – 50 OHM CHIP RESISTOR R10 Z8 C9 C10 C11 R4 R1 R2 R3 R9 R7 R8 R5, R7 – 47 K OHM CHIP RESISTOR (ADJUST FOR RATED Ic) R3, R4, R8, R9, 15 K OHM CHIP RESISTOR R5, 16 OHM CHIP RESISTOR R6, 1 K OHM CHIP RESISTOR Zo – 50 OHM MICROSTRIPLINE Z1–Z4 – ETCHED MICROSTRIPLINE CIRCIITRY Z5–Z8 – MICROSTRIP BIAS DECOUPLING LINES 4-11 The amplifier has a measured noise figure between 1.9 and 1.95 dB from 2400 to 2500 MHz with a nominal associated gain of 20 dB at a total current consumption of 2ÊmA for both devices. Measured output 1 dB gain compression point is -4.5 dBm with an associated IP3 of +7 dBm. See Figures 11 and 12. 2.3 2.2 2.1 2.0 1.9 1.8 1.7 NOISE FIGURE, dB 2,000 2,100 2,200 2,300 2,400 2,500 2,600 FREQUENCY, MHz Figure 11. AT-31011 Amplifier Noise Figure. 25 24 23 22 21 20 19 18 16 17 15 GAIN, dB 2,000 2,100 2,200 2,300 2,400 2,500 2,600 FREQUENCY, MHz Figure 12. AT-31011 Amplifier Gain. 6. Other Applications The low current bipolar transistors can also be used in frequency converter applications. Although not optimum, the 900 MHz amplifier circuit shown in Figure 4 can be used to demonstrate mixer operation. The amplifier circuit can be modified for use as a downconverter to a 10.7 MHz IF by simply coupling out the IF by attaching a 0.1 to 0.3 H coil to the output circuit. The point to couple to should be at the junction of C4 and C6 (reference Figure 2). Ultimately, the IF should also have a dc blocking capacitor but it was not required for this simple test. The LO is injected into the output port of the amplifier and the amplifier input port is the RF input port. With a nominal +3 dBm LO, the circuit without any optimization provides a nominal 6 dB conversion gain and less than 12 dB noise figure. Optimization of the bias and matching structures will improve performance. Generally, higher LO increases conversion gain but there is generally a nominal LO power that produces the lowest noise figure. Bias voltage and current can be critical, especially for lowest noise operation. 7. Matching Circuit Losses The losses associated with the input matching structure can be calculated with the help of equation (3) shown in the table below. The available gain of a two port is shown. The power delivered to the load is simply the power that would be delivered if the load were conjugately matched to the network. With the input to the network being 50 ohms, S = 0, equation (3) reduces to equation (4). The measurement of S21 is nothing more than a 50 ohm available gain measurement. It is imperative that the source and load presented to the device be as near a perfect 50Êohm impedance as possible as this is the reference impedance for the reflection coefficient. Both the numerator and the denominator use only the magnitude of S21 and L or S11 so it is only necessary to measure accurately the magnitude and not phase. With a network with a very high reflection coefficient, S22 becomes very large and S21 very lossy. With a low reflection coefficient, S22 is smaller and loss becomes very low. Several circuits are analyzed for loss and the results are shown in Table 2. The first circuit is a simple series inductor and blocking capacitor providing a noise match for a 900 MHz amplifier. Loss calculated to be 0.23 dB. The second circuit is a simple L network consisting of a variable series capacitor and a shunt inductor which transforms a 50 ohm source impedance to an S22 of 0.94 at 500ÊMHz. This is a typical reflection coefficient required to match both silicon and GaAs devices for lowest 2 2 G a = S 2 1 / (1 – L ) (4) 2 2 2 2 G a = S 21 11 S L (1 – S ) 1 – S (1 – ) (3) Equations 4-12 noise figure at 500 MHz. Compared to circuit number 1, the measured loss has increased 0.2 dB because of the losses associated with matching to a higher impedance. The third circuit is a parallel tuned circuit with a series input capacitor used to provide the high impedance transformation to a reflection coefficient of 0.85 at 150 MHz. Notice that the measured loss is the same as circuit number 1 with a similar reflection coefficient but at a different frequency. Circuits 4, 5, and 6 are micro-stripline designs for 900 and 2400 MHz.. Circuit 4 is the input network for the 900 MHz amplifier using the AT-32033 previously described. Subtracting the 0.26 dB for the input loss reduces the noise figure to 1 dB which is the noise figure as predicted without circuit losses. The loss of the input match for the 2400 MHz AT-31011 amplifier was measured at 0.44 dB. This is as a result of using lossy FR-4/G-G10 at 2ÊGHz and a higher reflection coefficient. Contrast this result with circuit number 6 which is a noise match for the ATF-10236 FET etched on ER = 2.2 material[6]. 8. Calculating Circuit Losses The calculation of circuit losses is only as accurate as the models of the individual circuit elements. The inductor in matching circuit #1 will be analyzed. The inductor used is an air wound solenoid with 5 turns #26 guage enamel wire with a 0.075″ I.D. The inductance is calculated as [7,8] : Table 2. Losses of Various Matching Networks. Circuit Freq. Circuit S21 S21 S22 S22 Loss Number (MHz) (dB) (dB) (dB) 1 900 L -5.8 0.513 -1.4 0.85 0.23 2 500 L/C -9.8 0.324 -0.54 0.94 0.45 3 150 Cap coupled -5.8 0.513 -1.4 0.85 0.23 tank 4 900 AT-32033 -0.5 0.944 -12.7 0.23 0.26 Microstrip 5 2400 AT-31011 -2.2 0.776 -4.75 0.58 0.44 Microstrip 6 2400 ATF-10236 -1.1 0.881 -7.0 0.45 0.14 Microstrip where n = number of turns r = radius l = length Solving yields L ~ 20 nH The unloaded Q can be calculated as follows: Qu = 2 r A f1/2 where r = radius A = 100 – 130 for 1/r from 2 to 20 f = frequency in MHz Solving yields Qu = 259. Actual measurements of Q suggest that a Qu of 100 to 200 might be a better value for maximum Qu. The equivalent series RS can now be calculated. Based on a Qu of 200 : Qu = Qu j lj lRs Therefore Rs = Solving yields RS = 0.565 . This is the equivalent series resistance of the 5 turn coil. The loaded Q of the circuit, Ql, can now be calculated or measured with the device terminating the matching network and a 50 source termination. The loaded Q can be found by dividing the 3 dB bandwidth into the nominal center frequency, fO. Another alternative is to plot Zin of the network terminated with the device. Any point on the Smith Chart represents an impedance consisting of both real and reactive components. Dividing the reactive part into the real part provides the Q of the network. The Ql is approximately 1 for this network. Network insertion loss can now be calculated with the following equation: Insertion Loss I.L. = -20 log [(Qu – Ql) / Qu] Solving yields an insertion loss of 0.043 dB. If the Qu of the inductor is only 100 then the loss would calculate at 0.087 dB, which is probably more consistent with the measured results. Other factors such as radiation loss, microstripline loss and capacitor Q can make up the difference in the calculated versus measured loss. 2 2 L (H) = n • r9 r + 10 l 4-13 Some packaged and molded inductors have a Qu of only 25 and with a higher Ql the loss can approach 0.5 dB! 9. Conclusions At low bias currents, the AT-3 series of devices can have a O as high as 0.94 at sub 1 dB noise figures. This allows the designer more flexibility in making tradeoffs and still achieving 1 to 1.5 dB noise figures at 900 MHz with silicon. In addition to concern over tuner losses and their effect ultimately on the accuracy of the noise parameter measurement, the losses associated with actual noise matching structures can approach 0.5 dB unless attention is paid to component Q.
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